Integrated circuit designs continue to increase in size and complexity, a bottom-up hierarchical design flow is becoming more common. In particular, system on a chip-type designs (“SOC”) incorporating a number of intellectual property cores (“IP cores” or “cores”) are increasingly common. SOCs are devices partially or wholly integrating various computer components into a monolithic semiconductor integrated circuit or a single package carrying several interconnected monolithic integrated circuits. “Chip” includes either configuration. An IP core is a reusable unit of logic, cell, or chip layout design that can be used as building blocks along with other logic to create a chip, including SOCs. Examples of IP cores include microprocessors such as those having ARM architectures, and peripheral controllers such as those for PCI Express, SDRAM, Ethernet, or USB devices. IP cores may be available as synthesizable register-transfer level (“RTL”), in a suitable hardware description language, or as gate-level logic in a netlisting language such as Verilog, or as physical layouts at a transistor level. IP cores are so named because a core is generally licensed from the vendor who is the party or entity that creates the IP core, and it is licensed by the circuit designer for use in the SOC.
In a bottom-up flow, the IP cores are separately designed and acquired, then integrated into an SOC. The IP core vendor can also create test patterns specific to a particular IP core, which can then be migrated for use in testing the SOC. The advantage of such an arrangement is that the test patterns are then portable along with the core, and may be used for any number of SOC designs incorporating that particular IP core. This simplifies test pattern generation for the SOC as a whole.
When a chip contains many instances of the same or identical core, it may be possible to produce a fully functional chip in which all instances of these identical cores are functional. It may also be possible to produce a less functional chip that has less than all instances of these cores working. Such a chip with only some working cores might sell for a lower cost than a fully functional chip, but that is much better than discarding chips that are mostly working and functional. Efficiently testing these chips, which may have a large amount of circuitry fabricated thereon, and efficiently identifying when a chip is fully good and functional, good enough to use with reduced function, or so bad and dysfunctional that it must be discarded, is a key challenge in the semiconductor industry.
SOCs may have instances of many different kinds of cores and more fundamentally, may have many instances of the same core. For example, processor cores, such as an ARM processor, might appear as four copies inside a cell phone SOC. Other SOC designs may have over one hundred instances of the same, identical core or IP block. To help improve the yield on these large SOC devices, the functional operation of the chip may be made to work in the presence of some number of non-functional cores when there are many instances of the same core. Those chips with fewer working cores may be sold for less money than those with the full complement of working cores. Alternatively, the system may only work with a certain number of cores, in which case as long as at least that many cores are functional, the chip may be said to be “fully working.” For example, a chip may be designed to contain 136 instances of a particular core, but at most 128 of these core instances will be used. So, there are allowed to be up to eight bad core instances before the chip would have to be discarded. This helps improve yield and makes more profit for the producer of the chip. This way of dealing with yield by including spare circuitry has been commonly used in memory chips and cores for many years, and has been successful at increasing yields for memories in general. SOCs and other chips using logic functions, in addition to memories, may also use this type of yield improvement technique.
In another example, the Cell processor chip may be used in a game console. The Cell chip had eight floating-point processor cores, but the software was designed to only ever use seven of the processors, as long as a chip had at least seven working floating-point processor cores, the chip could still be used in that game console; Cell chips with eight fully functional floating-point processors could be used in the game console as well, but could also be sold for higher revenue to a user that required all eight good floating point processors. This would greatly improve yields and reduce the cost of making the Cell processor chip, resulting in higher profit.
An issue with the ever-larger chip designs of today and tomorrow (i.e., chips with more and more circuitry) is that there is likely to be a large number of cores, and many identical instances of the same cores. During manufacturing test, it becomes important to detect when a failure is from a core that is allowed to be bad, i.e. a partially bad core type, and keep track of which and how many of each type of cores are bad.
One way to tell which core is bad is for the chip to be designed such that the test responses for each core are provided at a dedicated chip output pin for each core. This would allow manufacturing test to determine which core is bad based on which chip output pin has seen a failure. A problem with this approach is that with the increase in numbers of cores per chip, there may be more core instances than chip pins available for observing those cores; as a consequence, it is more challenging to track which core has tested “bad” over the course of applying the tests to the chip's cores. One alternative approach is to not test all cores at the same time. Rather, one may test only as many cores at one time as there are chip pins available to monitor simultaneously the outputs for the tested cores. This approach may be used, but is inefficient for testing a large number of identical cores on each chip.